View CXD4017R_4106313.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXD4017R
Reception Digital Signal Processor IC for Infrared Spatial Digital Audio Communication
Description The CXD4017R is an IC that processes the received digital signals used for infrared spatial digital audio communication (based on the IEC61603-8-1 standard) in consumer products. This IC contains the analog-to-digital converter (ADC) for RF signal applications and a PLL circuit for audio applications. Features * Performs all the received digital signal processing on a single chip. * Supports the infrared spatial digital audio communication system formats for consumer uses. * Direct input of RF signals enabled by on-chip ADC. * External RAM and PLL circuit not required. Demodulator Block * Digital processing throughout enables the received RF signals in the infrared spatial digital audio communication system formats to be processed directly. * External analog circuit can be simplified by digital filter and on-chip ADC for RF signal applications. * Reproduction of subcarrier processed digitally. Error Corrector Block * Enables error correction for infrared spatial digital audio communication system formats. Output Interface Block * Digital-to-analog converter (DAC) for various audio applications can be connected directly. Controller Block * Simple pin setting mode * Serial interface provided by serial bus * Enables output of error correction state. PLL Block * On-chip PLL circuit for reproducing the clock signals required by the infrared spatial digital audio communication system formats.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
64 pin LQFP (Plastic)
Structure Silicon gate CMOS IC Absolute Maximum Ratings * Supply voltage VDD1 -0.5 to +3.0 VDDE -0.5 to +3.0 * Input voltage VI -0.5 to VDDE + 0.5 ( 3.0V) * Output voltage VO -0.5 to VDDE + 0.5 ( 3.0V) * Storage temperature Tstg -55 to +125 Recommended Operating Conditions * Supply voltage VDDI 1.5 0.1 2.5 0.2 VDDE * A/D supply voltage VAD 2.5 0.2 * PLL supply voltage VPLL 1.5 0.1 * Operating temperature Topr -40 to +85
V V V V C
V V V V C
Input/Output Capacitance * Input capacitance CIN 16 (max.) pF * Output capacitance COUT 16 (max.) pF Note: Measurement conditions: Tj = 25C, VDD = VI = 0V, f = 1MHz * Analog input capacitance 12 (typ.) pF CAD
-1-
E03970B49-PS
CXD4017R
Block Diagram
APCPO PLVAR
18
PLREF
17
20 22
APVCI
23 APAVD OSCI 40 OSCO 43 PLL Clock Generator Clock Selector 24 APAVS 31 APX
28 VCOR 32 EXTCK
ADVRH ADAVS ADAVD ADVRL
6 7 8 9 A/D Converter Demodulator Error Corrector Output I/F
54 BCK 59 LRCK 60 DAOUT 61 DTVALID
ADVIN 10
62 EMPFS0 63 EMPFS1 13 XRST 14 DIFM0 15 DIFM1 29 CHNUM Buffer RAM 30 DIVCODE Controller 33 CSOD 34 SRDT 35 SWDT 36 XSCEN 37 SCLK 38 SCMODE 5 12 21 25 39 42 57 4 11 27 41 56 26 58
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDE
VDDE
VDDE
VDDE
VDDE
VDDI
Test pins not shown.
-2-
VDDI
CXD4017R
Pin Configuration
SCMODE
XSCEN
TEST4
TEST3
TEST2
TEST1
TEST0
OSCO
SWDT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TEST5 TEST6 TEST7 TEST8 TEST9 BCK TEST10 VDDE VSS VDDI LRCK DAOUT DTVALID EMPFS0 EMPFS1 TEST11
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
CSOD
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
SRDT
SCLK
OSCI
VDDE
VSS
VSS
EXTCK APX DIVCODE CHNUM VCOR VDDE VDDI VSS APAVS APAVD APCPO VSS APVCI TEST16 PLVAR PLREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADVRH
ADVRL
TEST12
TEST13
TEST14
ADAVS
ADAVD
ADVIN
XRST
VDDE
VSS
VDDE
VSS
DIFM0
DIFM1
-3-
TEST15
CXD4017R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol TEST12 TEST13 TEST14 VDDE VSS ADVRH ADAVS ADAVD ADVRL ADVIN VDDE VSS XRST DIFM0 DIFM1 TEST15 PLREF PLVAR TEST16 APVCI VSS APCPO APAVD APAVS VSS VDDI VDDE VCOR CHNUM DIVCODE APX EXTCK CSOD SRDT SWDT XSCEN SCLK I/O I I I -- -- I -- -- I I -- -- I I I I O O I I -- O -- -- -- -- -- I I I O I O O I I I Test pin, normally fixed at low Test pin, normally fixed at high Test pin, normally fixed at high Digital I/O power supply Digital GND RF ADC reference voltage input (high) RF ADC analog GND RF ADC analog power supply RF ADC reference voltage input (low) RF ADC input Digital I/O power supply Digital GND Reset (negative logic) Audio output format selection Test pin, normally fixed at low PLL reference output (fs) PLL frequency-divided output (APX output or VCOR input divided by 256) Test pin, normally fixed at low PLL VCO control voltage input Digital GND PLL charge pump output PLL VCO power supply PLL VCO GND Digital GND Digital internal power supply Digital I/O power supply Data output clock input Channel number selection (low: Ch0, high: Ch1) Full/half-band mode selection (low: full-band, high: half-band) PLL VCO output Data output clock selection (low: APX internal connection, high: VCOR pin input) Chapter start delay output Serial interface data read output Serial interface data write output Serial interface data enable input (negative logic) Serial interface data clock input -4- Description
CXD4017R
Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol SCMODE VSS OSCI VDDE VSS OSCO TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 BCK TEST10 VDDE VSS VDDI LRCK DAOUT DTVALID EMPFS0 EMPFS1 TEST11
I/O I -- I -- -- O I I I I I I I I O O O O -- -- -- O O O O O I
Description Control mode selection (low: pin setting, high: serial setting) Digital GND Crystal oscillator circuit input (12.288MHz) Digital I/O power supply Digital GND Crystal oscillator circuit output (12.288MHz) Test pin, normally fixed at low Test pin, normally fixed at low Test pin, normally fixed at low Test pin, normally fixed at low Test pin, normally fixed at low Test pin, normally fixed at low Test pin, normally fixed at low Test pin, normally fixed at low Test pin, normally open Test pin, normally open Bit clock output Test pin, normally open Digital I/O power supply Digital GND Digital internal power supply Audio sample clock output Output data for audio DAC Data valid flag output (DTVALID, low: invalid, high: valid) Emphasis, fs information output Test pin, normally fixed at high
-5-
CXD4017R
Electrical Characteristics 1. DC characteristics Item High level input voltage Low level input voltage High level output voltage Low level output voltage High level output current Low level output current Input leakage current Crystal connection pin Symbol VIH VIL VOH VOL IOH IOL IL VIL VPLL VCPO VVCI VAD VRH VRL VRW RRW VIA CAD VOFF VDDI = 1.5V VDDE = 2.5V VAD = 2.5V VPLL = 1.5V VRW = 2.0V IOH = -100A IOL = 100A VOH = VDDE - 0.4V VOL = 0.4V (VDDE = 2.5 0.2V, VDDI = 1.5 0.1V, VSS = 0V, Topr = -40 to +85C) Conditions Min. 1.7 -0.3 VDD - 0.2 0 -4.0 -8.0 4.0 8.0 -- 1.7 -0.3 1.4 0 0 2.3 1.0 0.0 1.0 140 VRL 2.5 2.0 -- 2.0 280 -- 12 20 7.5 3.2 6.7 0.5 7.2 14.3 mA VRH 1.5 Typ. -- -- -- -- -- -- -- -- -- Max. VDDE + 0.3 0.7 VDDE 0.2 -- -- -- -- 5 VDDE + 0.3 0.7 1.6 VPLL VPLL 2.7 VAD VAD - 1.0 2.1 A V V V V V V V V 10 V V pF mV 12 13 9 6 10 11 mA V 2, 3, 4 2, 3 4 2, 3 4 1 5 5 6 7 8 9 Unit Applicable pins 1
High level VIH Low level
PLL supply voltage PLL charge pump output voltage PLL VCO control voltage ADC supply voltage ADC reference voltage (high) ADC reference voltage (low) ADC reference potential difference (1) ADC reference input resistance (2) ADC input voltage ADC input capacitance ADC offset
Digital block supply current IDDI internal logic Digital block supply current IDDE I/O ADC block supply current PLL block supply current Reference voltage pin current of A/D block IAD IPLL IREF
Note 1: VRW = VRH - VRL Note 2: A current of approximately 7.2mA (typ.), 14.3mA (max.) flows between the ADVRH pin and ADVRL pin (when VRW is 2.0V). Ensure that the drive capacity of the supply power concerned is adequate. -6-
CXD4017R
Applicable pins 1 XRST, DIFM0, DIFM1, VCOR, CHNUM, DIVCODE, EXTCK, SWDT, XSCEN, SCLK, SCMODE, TEST0 to TEST7, TEST11 to TEST16 2 CSOD, LRCK, DAOUT, DTVALID, EMPFS0, EMPFS1, TEST8 3 SRDT 4 PLREF, PLVAR, APX, BCK, TEST9, TEST10 5 OSCI, OSCO 6 APAVD, APAVS 7 APCPO 8 APVCI 9 ADAVD, ADAVS 10 ADVRL, ADVRH 11 ADVIN 12 VDDI 13 VDDE
-7-
CXD4017R
2. AC characteristics (1) OSCI, OSCO pins (a) When using self-excited oscillation (VDDE = 2.5 0.2V, VDDI = 1.5 0.1V, VSS = 0V, Topr = -40 to +85C) Item Oscillation frequency Symbol fSYS Min. -- Typ. 12.288 Max. -- Unit MHz
(b) When inputting pulses to OSCI (VDDE = 2.5 0.2V, VDDI = 1.5 0.1V, VSS = 0V, Topr = -40 to +85C) Item Pulse frequency High level pulse width Low level pulse width Rise time/fall time Symbol fSYS Min. -- -- -- Typ. 12.288 40.69 40.69 Max. -- -- -- 5 Unit MHz ns ns ns
tWHX tWLX tR, tF
tCX (1/fSYS) tWHX
tWLX VIHX VIHX x 0.9
OSCI
VDDE/2 VIHX x 0.1 VILX tR tF
(2) VCOR pin Item Pulse frequency
(VDDE = 2.5 0.2V, VDDI = 1.5 0.1V, VSS = 0V, Topr = -40 to +85C) Symbol fCXR Min. 8.176 Typ. -- -- -- Max. 12.31 Unit MHz ns ns
High level pulse width Low level pulse width
tWHXR tWLXR
tCXR x 0.4 tCXR x 0.4
tCXR (1/fCXR)
tCXR x 0.6 tCXR x 0.6
tWHXR
tWLXR VIHX VIHX x 0.9
VCOR
VDDE/2 VIHX x 0.1 VILX tR tF
-8-
CXD4017R
(3) SCLK, XSCEN, SWDT, SRDT pins (VDDE = 2.5 0.2V, VDDI = 1.5 0.1V, VSS = 0V, Topr = -40 to +85C) Item Clock period Symbol Min. 800 400 400 170 0 400 350 350 -- 162 -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- 345 -- 80 Unit ns ns ns ns ns ns ns ns ns ns ns
tCW Clock pulse width, high tCWH Clock pulse width, low tCWL Enable signal pulse width tCSWH Enable signal setup time tCSS Enable signal hold time tCSH Setup time tWSU Hold time tWHD Access time tAC Enable time tOLZ Disable time tOHZ
tCW tCSS XSCEN tCWL tCWH tCSH tCSWH
SCLK tWSU tWHD
SWDT
An Example of DATA READ Phase
Hi-Z SRDT tAC tOLZ Valid tAC Valid tOHZ
Hi-Z
-9-
CXD4017R
(4) CSOD pin Item CSOD pulse width
(VDDE = 2.5 0.2V, VDDI = 1.5 0.1V, VSS = 0V, Topr = -40 to +85C) Symbol Min. 30 Typ. -- Max. -- Unit s
tCSOD
CSOD tCSOD
(5) XRST pin Item XRST pulse width
(VDDE = 2.5 0.2V, VDDI = 1.5 0.1V, VSS = 0V, Topr = -40 to +85C) Symbol Min. 10.0 Typ. -- Max. -- Unit ns
tXRST
XRST tXRST
- 10 -
CXD4017R
Description of Functions 1. Description of clock generator (1) This LSI chip can generate the system clock pulse by connecting a 12.288MHz crystal oscillator to the OSCI pin and OSCO pin. (2) It functions as the system clock by inputting a 12.288MHz external oscillation clock pulse to the OSCI pin while keeping the OSCO pin open.
2. Description of PLL circuit (1) In addition to supplying the system clock pulse using the OSCI pin, this LSI requires the reproduction clock pulse which is provided by the PLL circuit. The PLL circuit provided on the LSI chip can be used for this purpose. (2) If the sampling frequency of the digital audio signals which contain the input RF signal is fs, then the reproduction clock pulse provided by the PLL circuit has a frequency of 256fs. (3) When the PLL circuit on the LSI is used, input a low level to the EXTCK pin and VCOR pin. Furthermore, an external lag-lead filter must be connected to the LSI between the charge pump output APCPO pin and the VCO control voltage input APVCI pin of the PLL circuit. Ensure that the wiring involved is kept as short as possible. (4) When the PLL circuit on the LSI is not used, the LSI chip must be provided with an external PLL circuit. Input a high level to the EXTCK pin and the reproduction clock pulse to the VCOR pin. The reference signal of the PLL circuit for generating the clock pulses is output to the PLREF pin, and its frequency is set to fs. At this time, the frequency of the clock pulse which has been input to the VCOR pin is divided by 256 inside the LSI, and the pulse with the resulting frequency is output to the PLVAR pin.
- 11 -
CXD4017R
3. Pin setting/serial setting mode The setting modes of this LSI can be broadly classified into two: the pin setting mode and the serial setting mode. Switching between these modes is achieved by the SCMODE pin. Pin SCMODE Signal level Low High Operation Pin setting mode Serial setting mode
The pins of this LSI that become not significant in serial setting mode are listed below: DIVCODE pin, CHNUM pin, DIFM0 pin, DIFM1 pin In the serial setting mode, these pins can be set by serial setting. The rated values of the parameters which cannot be changed in pin setting mode (they can be changed in serial setting mode) are given below. Parameter CRCCK XMUTE Rated value 1 1 Operation CRC checked. Not muted
CRCCK is valid only when crc_flag on Source_Info is set to "1", and when the CRC check is performed, the CRC errors affect the output data. (1) Pin setting mode In the pin setting mode (SCMODE = low), this LSI enables the various LSI operations to be changed by the DIVCODE pin, CHNUM pin, DIFM0 pin and DIFM1 pin. (2) Serial setting mode In serial setting mode (SCMODE = high), this LSI enables the various LSI operations to be changed by the serial interface.
- 12 -
CXD4017R
4. Description of serial interface (1) Serial interface timings This LSI enables the various LSI operations to be changed by the SCLK pin, SWDT pin, XSCEN pin and SRDT pin. The serial interface is divided into two code groups called the write code and read code. The interface timing chart for each code group is presented below. (2) XRST pin All the internal registers are initialized to "0" when reset by setting the XRST pin to low. (3) SRDT pin SRDT is the tri-state output pin. In order to use this pin as a quasi open drain output, the external pull-up supply voltage must be set to less than VDDE. Furthermore, the external pull-up resistance must be set to a value which is within the output drive capacity (IOL = 4mA).
XSCEN
SCLK
SWDT
A7
A6
A5
A4
A3
A2
A1
A0 Dn - 1 Dn - 2 Dn - 3
D2
D3
D2
D1
D0
Internal Registers
Valid
Write Code
XSCEN
SCLK
SWDT
A7
A6
A5
A4
A3
A2
A1
A0
Hi-Z SRDT
Dn - 1 Dn - 2
D1
D2
D3
D2
D1
D0
Hi-Z
Read Code
- 13 -
CXD4017R
(4) Serial setting command table Address [A7 to A0] Code Command bit width Name [Dn - 1 to D0] DIVCODE CHNUM 0000_0000 (00h) Write 8 XMUTE CRCCK1 DIFM res. 1000_0110 (86h) Read 8 CORNUM2 Bit width 1 1 1 1 3 1 8 -- Value 0 1 0 1 0 1 0 1 -- Effect Full-band mode Half-band mode Lower band Higher band Muted Not muted CRC not checked CRC checked DAOUT output format selected Reserved Number of corrections in chapter
1 CRCCK is valid only when crc_flag on Source_Info is set to "1", and when the CRC check is performed, the CRC errors affect the output data. 2 This is the number of corrections in one chapter obtained from ECC.
- 14 -
CXD4017R
5. Description of audio DAC interface (1) In this LSI, the audio DAC can be directly coupled. If the on-chip PLL circuit is used, a 256fs clock pulse is output to the APX pin. DAOUT: DAC data BCK: DAC bit clock pulse LRCK: DAC sample clock pulse DTVALID: Data valid flag (low: invalid, high: valid) (2) The emphasis and sampling frequency information is output to the EMPFS0 pin and EMPFS1 pin. EMPFS1 Low Low High High EMPFS0 Low High Low High Emphasis Not provided Provided Provided Provided Sampling frequency No information 44.1kHz 48kHz 32kHz
(3) The data valid flag DTVALID indicates the valid_flag contained in the Source_Info and the errors in communication. When this pin is low, it indicates that the valid_flag is "0" or that some kind of error, including any errors in the input signals at the transmission end, has occurred at some point after these signals were input. (4) Sixty-four BCK cycles are contained in one LRCK cycle. (5) The DAOUT output format can be changed by the DIFM register (3 bits) with address 00h when SCMODE is high (serial setting mode) and by the DIFM1 pin and DIFM0 pin when SCMODE is low (pin setting mode). SCMODE = High DIFM 000 001 010 011 100 101 110 111 No settings possible SCMODE = Low DIFM1 Low Low High High DIFM0 Low High Low High
Output mode Mode-0 Mode-1 Mode-2 Mode-3 Mode-4 Mode-5 Mode-6 Mode-7
- 15 -
CXD4017R
Output mode Mode-0 Mode-1 Mode-2 Mode-3 Mode-4 Mode-5 Mode-6 Mode-7
Data output format Full-band MSB first, Left Justified I 2S MSB first, 16 bits, Right Justified MSB first, 24 bits, Right Justified MSB first, 20 bits, Right Justified LSB first, Right Justified --1 --1 Half-band MSB first, Left Justified I2S MSB first, 16 bits, Right Justified MSB first, 16 bits + 8 bits (zero data), Right Justified MSB first, 16 bits + 4 bits (zero data), Right Justified LSB first, Right Justified LSB first, Right Justified
1 Connection cannot be made to the DAC since these are special formats. 2 In modes 0 to 5, the data is output only when pcm_id on the Source_Info is output. Timing charts covering what has been described above are presented below. Audio DAC interface timing charts
LRCK BCK DAOUT MSB
Left Channel
LSB
Full-band, Mode-0
LRCK BCK DAOUT MSB LSB Left Channel
Full-band, Mode-1
LRCK BCK DAOUT MSB LSB
Left Channel
Full-band, Mode-2
LRCK BCK DAOUT MSB LSB Left Channel
Full-band, Mode-3 - 16 -
CXD4017R
LRCK BCK DAOUT
Left Channel
MSB
LSB
Full-band, Mode-4
LRCK BCK DAOUT LSB
Left Channel
MSB
Full-band, Mode-5
LRCK BCK DAOUT free_field LSB
Left Channel
MSB
Full-band, Mode-6
LRCK BCK DAOUT free_field LSB
Left Channel
MSB V U C P
Full-band, Mode-7
LRCK BCK DAOUT MSB
Left Channel
LSB
Half-band, Mode-0
LRCK BCK DAOUT MSB
Left Channel
LSB
Half-band, Mode-1
LRCK BCK DAOUT
Left Channel
MSB
LSB
Half-band, Mode-2 - 17 -
CXD4017R
LRCK BCK DAOUT MSB
Left Channel
LSB
Half-band, Mode-3
LRCK BCK DAOUT
Left Channel
MSB
LSB
Half-band, Mode-4
LRCK BCK DAOUT
Left Channel
LSB
MSB
Half-band, Mode-5, 6, 7
- 18 -
CXD4017R
6. Description of other functions (1) Mute conditions The conditions under which muting occurs are more or less as listed below. * When the RF signal cannot be received due to cutoff or some other such reason In this case, the signal is muted as soon as it could not be received. * When many errors have occurred due to poor reception In this case, the signal is muted as soon as it is deemed that a high number of errors have occurred. * When the prescribed time has not elapsed after the signal was muted due to cutoff or some other such reason In this case, the muting is released after the prescribed time has elapsed since it was deemed that the RF signal received is problem-free. * When the PLL lock was not applied The muting is released after the prescribed time has elapsed since the PLL lock was applied. * When the XMUTE pin was set to "0" at address 00h In this case, the signal is instantly muted immediately after the setting. The muting is instantly released immediately after the XMUTE pin is set to "1". (2) CSOD The read parameters of the Read Code based on the serial interface are updated on a chapter by chapter basis in the infrared spatial digital audio communication system format. The CSOD pin output indicates a break in the chapter in response to the issue of this command. Access the Read Code within 3ms after the CSOD pin has changed from high to low. (3) CORNUM Feed forward errors are corrected in the infrared spatial digital audio communication system format. At the reception end, the errors are corrected using this parity. The number of symbols (bytes) whose errors have been corrected this way can be counted up. The number obtained by the countup for each chapter is output as the CORNUM. CORNUM takes the following values. Name CORNUM Min. 0 Value Max. 165
(4) DTVALID This signal, which is the data valid flag, is set to high when all of the following conditions have been met. * The number of times errors cannot be corrected in a chapter in the error correction circuit must not exceed 2. * No CRC errors must have occurred. (Operation can be changed by serial interface address 00h and CRCCK.) * The SYNC pattern of the received signals must have been detected properly. * The digital audio sample frequency must be locked. * The header signals among the received signals must coincide in multiple ways. * The synchronization timing in the output interface block must be locked to the start of the chapter of the received signals. * The XMUTE internal signal described above must be set to "1" (XMUTE is "1" when SCMODE is at low, and its setting can be changed by the serial interface when SCMODE is at high). - 19 -
CXD4017R
7. Application Circuit
X'tal 12.288MHz 2.5VD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TEST4
XSCEN
OSCO
49
SCMODE
TEST3
TEST2
TEST1
TEST0
SWDT
TEST5 50 TEST6 51 TEST7 52 TEST8 53 TEST9 54 BCK 55 TEST10 56 VDDE 1.5VD 57 VSS 58 VDDI 59 LRCK 60 DAOUT 61 DTVALID 62 EMPFS0 63 EMPFS1 CXD4017R
SRDT CSOD
VDDE
SCLK
OSCI
VSS
VSS
32 EXTCK APX 31
DIVCODE 30 CHNUM 29 VCOR 28 VDDE 27 VDDI 26 VSS 25 APAVS 24 APAVD 23 APCPO 22 VSS 21 APVCI 20 TEST16 19 PLVAR 18 PLREF 17 1.5VA 1.5VD
TEST12 TEST13
TEST14
ADVRH
ADAVD
ADAVS
ADVRL
ADVIN
VDDE
Audio D/A Convertor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DIFM0
XRST
VDDE
64
15
Lch 2.0VA (Reference Voltage) Rch
2.5VA
Reset Circuit
CXA3504M
I/V Converter
BPF
AGC
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 20 -
DIFM1 TEST15
TEST11
VSS
VSS
16
CXD4017R
Notes on Operation * The loop filter portion of the PLL block is important for the characteristics. Therefore, the loop filter should be located as close to the IC pin as possible and surrounded by AGND. In addition, temperature compensation parts should be used for the loop filter capacitor and resistor. * The CXD4017R generates a delay during reception. Labeling the sampling frequency as fs, the delay time is 384/fs [s] in full-band mode. For example, when fs = 48kHz, the delay time is 8ms. In addition, in half-band mode the delay time is 768/fs [s]. In this case for example, when fs = 48kHz, the delay time is 16ms. Note that a delay is also generated during transmission by the transmission side IC CXD4016R. See the CXD4016R data sheet for details. CXD4017R Evaluation Board Description The CXD4017R evaluation board is a dedicated board designed to allow easy evaluation of the CXD4017R which was developed for reception of infrared spatial digital audio communication. An infrared spatial digital audio communication system format RF signal which is input from a SMB connecter is demodulated to a digital audio signal, and is converted to an analog audio signal by an internal audio DAC, then is output as pin jack or headphone output. The number of corrections can be displayed on the LED, so the receiving state can be confirmed visually. Features * Supply voltage: 5V power supply * Displays the number of corrections on the LED * 2 audio outputs; pin jack and headphone output Operating Conditions * Supply voltage: 5V (typ.) * Current consumption: +5V: 180mA (typ.), -5V: 10mA (typ.) Operation Method The CXD4017R evaluation board allows easy evaluation simply by providing the power supply and inputting an infrared spatial digital audio communication system format RF signal. The evaluation procedure is as follows. (1) Connect the power supply to the power supply connection pin J6. (2) SW1 is the manual reset switch. A reset is applied automatically during power-on, but this switch is used to perform reset manually. (3) The DIVCODE pin can be set by DIP switch S1-1. The DIVCODE pin is set low when this switch is OFF, and high when ON. (4) The CHNUM pin can be set by DIP switch S1-2. The CHNUM pin is set low when this switch is OFF, and high when ON. (5) The SCMODE pin can be set by DIP switch S1-3. The SCMODE pin is set low when this switch is OFF, and high when ON (6) The DIFM2 pin can be set by DIP switch S1-4. The DIFM2 pin is set low when this switch is OFF, and high when ON (7) The DIFM1 pin can be set by DIP switch S1-5. The DIFM1 pin is set low when this switch is OFF, and high when ON (8) The DIFM0 pin can be set by DIP switch S1-6. The DIFM0 pin is set low when this switch is OFF, and high when ON - 21 -
CXD4017R
(9) Always set DIP switches other than noted above to OFF. The above contents are listed in the tables below for reference. S1 1 2 3 4 5 6 7 8 Mode OFF: DIVCODE = L, ON: DIVCODE = H OFF: CHNUM = L, ON: CHNUM = H OFF: SCMODE = L, ON: SCMODE = H OFF: DIFM2 = L, ON: DIFM2 = H OFF: DIFM1 = L, ON: DIFM1 = H OFF: DIFM0 = L, ON: DIFM0 = H Always OFF Always OFF
S2 1 2 3 4 5 6 7 8
Mode Always OFF Always OFF Always OFF Always OFF Always OFF Always OFF Always OFF Always OFF
(10) Light emitting diode D1 is off when DIVCODE is low, and lighted when DIVCODE is high. (11) Light emitting diode D2 is off when CHNUM is low, and lighted when CHNUM is high. (12) Light emitting diodes D3 and D4 indicate the sampling frequency of the audio signal. This relationship is shown in the table below. D3, D4 Off, off Off, lighted Lighted, lighted Flashing, flashing Sampling frequency 44.1kHz 48kHz 32kHz Unlock
(13) Light emitting diodes D5 to D8 are not used.
- 22 -
CXD4017R
(14) Light emitting diodes D9 to D15 display the number of error corrections. This is the total error correction numbers during time for 48 chapters. The relationship between lighting of light emitting diodes and the number of error corrections is shown in the table below. D9 D10 D11 D12 D13 D14 D15 Lighted with 1 error correction or more Lighted with 3 error corrections or more Lighted with 9 error corrections or more Lighted with 27 error corrections or more Lighted with 81 error corrections or more Lighted with 243 error corrections or more Lighted with 729 error corrections or more
(15) Light emitting diode D16 is off when DTVALID is high, and lighted when DTVALID is low. (16) Connection pins J3,J4, J7 and J9 are not used. (17) Audio signal outputs LINE OUT and Headphone OUT are available. For headphone OUT, the output level can be adjusted by RV1.
CXD4017R EVB Semiconductor Parts List Parts No. U1, 5 U2, 4 U3 U6 U7 U8 U9, 10, 11 U12, 13 U14 Q1 D1, 2, 9, 10 D3, 4, 11, 12 D5, 6, 13, 14 D7, 8, 15, 16 D17 to 22 Product name NJM5532M TC74HCT541F AK4393VF EP1K100QI208-2 EPC2LI20 CXD4017R LM317T TL7705CP TC74LCX541F 2SC2223L TLG124 TLY124 TLO124 TLR124 1S1588 Toshiba Asahi Kasei Microsystems ALTERA ALTERA SONY National Semiconductor Texas Instruments Toshiba NEC Toshiba Toshiba Toshiba Toshiba Toshiba Manufacturer New Japan Radio
FPGA Operation (1) Accumulates the number of error corrections, and displays. (2) Detects the sampling frequency. - 23 -
Circuit Diagram
RF DIVCODE MAIN2 DTVALID ADVIN ADVIN CLK EMPFS0 EMPFS1
MAIN1 DIVCODE
DTVALID CLK EMPFS0 EMPFS1
SWDT XSCEN SCLK SRDT CSOD
SWDT XSCEN SCLK SRDT CSOD LRCK0 BCK0 DAOUT0 LRCK1 BCK1 DAOUT1 LRCK1 BCK1 DAOUT1 AUDIO
- 24 -
POWER
LRCK0 BCK0 DAOUT0
APX0 SWDIF0 PWXRST SWDIF1 DTSEL XRSTPW2 XRSTPW2 SCMODE SWCHNUM SWDIVCODE
APX0 SWDIF0 SWDIF1 DTSEL SCMODE SWCHNUM SWDIVCODE
APX1
APX1
DIF0 DIF1 DIF2 DEM0 DEM1 SMUTE
DIF0 DIF1 DIF2 DEM0 DEM1 SMUTE DFS PDX
XRSTPW2 XRSTPW1 XRSTPW1
DFS PDX
CXD4017R
CXD4017R EVB Circuit Diagram (TOP)
R1 470 +A5V
J1 RCA JACK 2P
3 2
Rch (RED) Lch (WHITE)
1
C1 470/10V
R2 470
R3 1k R5 1k C4 3300p
R4 1k
C2 0.1 C3 1000p
+D5V C5 0.1 U2 APX1 PDX BCK1 DAOUT1 D2.5V 1 2 3 4 5 6 7 8 9 10 G1 VCC G2 A1 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 GND Y8 74HCT541F C9 0.1 R13 4.7k R14 4.7k R15 4.7k U4 LRCK1 SMUTE DFS DEM0 DEM1 DIF0 DIF1 DIF2 R19 4.7k R20 4.7k R21 4.7k 1 2 3 4 5 6 7 8 9 10 G1 VCC G2 A1 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 GND Y8 74HCT541F 20 19 18 17 16 15 14 13 12 11 C12 0.1 +D5V +A5V U3 C11 10/16V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DVSS DVDD MCLK PD BICK SDATA LRCK SMUTE DFS DEM0 DEM1 DIF0 DIF1 DIF2 CKS2 CKS1 CKS0 P/S VCOM AOUTL+ AOUTL- AOUTR+ AOUTR- AVSS AVDD VREFH VREFL BVSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C13 0.1 C14 10/16V 20 19 18 17 16 15 14 13 12 11 R6 1k
8
3
3
2
RV1A 20k
1
R11 47k
C8 470/10V -A5V
R12 4.7k
C10 10/16V J2
3 2 1
4
R7 1k R10 1k
1 2
R8 47k
8
5 7 6
R9 100
C6 1000p
U1A NJM5532M C7 0.1
U1B NJM5532M
4
8
3
8
4
6
5
RV1B 20k
4
R27 47k C22 0.1
R28 4.7k C24 10/16V -A5V
4
- 25 -
PHONEJACK STEREO +A5V R16 1k C15 0.1 C16 10/16V C20 3300p R18 1k R17 1k C18 1000p C17 0.1
AK4393VF
R22 1k
R23 1k R26 1k
1 2
R24 47k
C19 470/10V
5 7 6
R25 100
C21 1000p
U5A NJM5532M
U5B NJM5532M
C23 470/10V
CXD4017R EVB Circuit Diagram (AUDIO)
CXD4017R
J3 IFdata10 IFdata9 IFdata8 10 9 8 7 6 5 4 3 2 1 GND A9 GND A7 GND A5 GND A3 GND A1
IFdata10
IFdata5
IFdata4
IFdata3
IFdata2
IFdata9
IFdata8
IFdata7
IFdata6
CLK
IFdata1
IFdata7 D2.5V IFdata6
1 2 3 4 5 6 7 8 9
TH1 TH C25 0.1
TH2 TH C26 0.1
TH3 TH
TH4 TH C27 0.1 C28 0.1
TH5 TH6 TH TH IFdata5 ALT3.3V ALT3.3V IFdata4 IFdata3
RA1 M9-1-103J 10 9 8 7 6 5 4 3 2 1
COM R1 R2 R3 R4 R5 R6 R7 R8
IL-10P-S3EN2
J4 GND A9 GND A7 GND A5 GND A3 GND A1
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
R29 10k
R30 1k
IFdata2 IFdata1
nCS CS nWS IFdata10 nRS IFdata9 I_O VCCINT IFdata8 I_O IFdata7 I_O IFdata6 I_O VCCIO I_O I_O I_O I_O I_O GND I_O I_O VCCINT Ded_Input CLK Ded_Input GND I_O I_O VCCIO I_O I_O I_O IFdata5 I_O IFdata4 GND IFdata3 I_O IFdata2 IFdata1 I_O VCCIO I_O I_O I_O I_O I_O I_O I_O I_O
1 2 3 4 5 6 7 8 9
TP4 LC-2S-Y SCLK
1
TP1 LC-2S-Y SCMODE C29 0.1
1
EMPFS1 EMPFS0 DTVALID DAOUT0 LRCK0 BCK0 SCMODE SCLK TP3 LC-2S-Y SWDT
1
1
R32 R34 R45 R44 C33 0.1 R42 R43 C35 0.1
1
TH7 TH
R38 R33 TP2 LC-2S-Y XSCEN
1
100 C32 0.1
100
XSCEN SWDT SRDT CSOD R35
R36 100
100
C34 0.1
SWDIVCODE TP8 LC-2S-Y DTSEL
1
R48
100 C36 0.1 C38 0.1 TH8 TH TH10 TH C40 0.1 TH11 TH
SWCHNUM DTSEL SWDIF1 SWDIF0 DIVCODE R47
R46 R37 R41 R40 100
100 100 100 100
DSW1_1 DSW1_2
100 LED1
100 LED2
100 LED3
100 LED4
100 LED5
100 LED6
100 LED7
100 LED8
I_O I_O DSW1_3 DSW1_4 DSW1_5 DSW1_6 GND DSW1_7 DSW1_8 LOCK DSW2_1 I_O DSW2_2 VCCIO DSW2_3 DSW2_4 DSW2_5 DSW2_6 RMCK VCCINT I_O I_O I_O GND VCC_CKLK XRSTPW2 GlobalCLK1 Ded_Input GND_CLK GND DSW2_7 VCCIO DSW2_8 I_O LED9 LED10 I_O LED11 VCCINT LED12 I_O LED13 I_O LED14 LED15 VCCIO I_O LED16 I_O LED1 I_O LED2
C42 0.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
TCK CONF_DONE nCEO TDO VCCIO GND EMPFS1 I_O EMPFS0 I_O DTVALID I_O DAOUT0 I_O LRCK0 BCK0 SCMODE SCLK INIT_DONE GND VCCINT VCCIO GND XSCEN I_O SWDT SRDT CSOD I_O I_O SWDIVCODE GND VCCINT VCCIO GND SWCHNUM DTSEL I_O SWDIF0 I_O SWDIF1 VCCIO GND DIVCODE DSW1_1 I_O DSW1_2 VCCINT GND TMS TRST nSTATUS
U6 EP1K100QI208-2_1
DATA0 DCLK nCE TDI VCCINT GND APX1 PDX BCK1 I_O VCCIO GND DAOUT1 LRCK1 I_O I_O SMUTE DFS VCCIO GND I_O I_O DEM0 I_O DEM1 I_O VCCINT GND DIF0 I_O DIF1 DIF2 VCCINT GND LED8 I_O LED7 I_O VCCIO GND LED6 LED5 I_O LED4 I_O LED3 VCCIO GND MSEL0 MSEL1 VCCINT nCONFIG
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
TP5 LC-2S-Y APX1 C30 0.1
1
TP9 LC-2S-Y BCK1
1
RA2 M9-1-103J APX1 PDX BCK1
R31 R49 R39
22 100 100
C31 0.1
TP6 LC-2S-Y DAOUT1 100 100 100 100
TP7 LC-2S-Y LRCK1 DAOUT1 LRCK1 SMUTE DFS
100 100
DEM0 DEM1
R50 R51 R52
100 100 100
DIF0 DIF1 DIF2
C37 0.1
LED8 LED7 TH TH9 LED6 LED5 LED4 LED3 TP10 LC-2S-BK DGND TP11 LC-2S-BK DGND
C39 0.1
1
COM R1 R2 R3 R4 R5 R6 R7 R8
IL-10P-S3EN2
C41 0.1 C43 0.1 XRSTPW1
R53
R54
R55
R56
R57
R58
R59
R60
D5
D6
D7
D1
D2
D3
D4
D8
3 2 1 20 19
ALT3.3V TH13 TH C49 0.1 C45 0.1 C46 0.1 C47 0.1 C48 0.1 TH15 TH U7 R61 10k
COM R1 R2 R3 R4
TH12 TH TH14 TH C44 0.1
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
RA3 M5-1-102J ALT3.3V
FULL/HALF TLG124A
CHNM TLG124A
STA_5 TLO124
STA_6 TLO124
STA_7 TLR124
Fs_1 TLY124
D2.5V
Fs_0 TLY124
STA_8 TLR124
LED10
LED11
LED12
LED13
LED14
LED15
LED16
4 5 DCLK 6 VCCSEL 7 NC 8 NC OE
TCK DATA TDO VCC TMS
18 VPP 17 NC 16 NC 15 NC 14 VppSel C51 0.1 R70 1k
1 2 3 4 5
ALT3.3V
R62
R63 D10
R64 D11
R65 D12
R66 D13
R67 D14
R68 D15
R69 D16
RA4 R8 R7 R6 R5 R4 R3 R2 R1 COM 9 8 7 6 5 4 3 2 1 DSW1_8 DSW1_7 DSW1_6 DSW1_5 DSW1_4 DSW1_3 DSW1_2 DSW1_1 8 7 6 5 4 3 2 1
ON S1 9 10 11 12 13 14 15 16 A6E-8104
D2.5V XRSTPW2 APX0
RA5 R8 R7 R6 R5 R4 R3 R2 R1 COM 9 8 7 6 5 4 3 2 1 DSW2_8 DSW2_7 DSW2_6 DSW2_5 DSW2_4 DSW2_3 DSW2_2 DSW2_1 8 7 6 5 4 3 2 1
ON S2
D2.5V 9 10 11 12 13 14 15 16
EPC2LI20
STA_9 TLG124A
D9
STA_11 TLY124
STA_12 TLY124
STA_13 TLO124
STA_14 TLO124
STA_15 TLR124
STA_16 TLR124
D2.5V
STA_10 TLG124A
9 10 nCS 11 GND 12 TDI 13 nCASC nInt_Conf
LED9
LED9 LED10
LED11
LED12
LED13
LED14 LED15
DSW1_3 DSW1_4 DSW1_5 DSW1_6
DSW1_7 DSW1_8
DSW2_1
DSW2_2
DSW2_3 DSW2_4 DSW2_5 DSW2_6
DSW2_7
DSW2_8
LED16
1 3 5 7 9
100
100
100
100
100
100
100
100
TCK GND 2 TDO Vcc 4 TMS NC 6 NC NC 8 TDI GND 10 J5 XG4C-1031
1
LED1
LED2
- 26 -
C50 0.1
CXD4017R
A6E-8104
M9-1-103J
M9-1-103J
CXD4017R EVB Circuit Diagram (PLD)
TP42 LC-2S-Y TXOUT/RINFO
1
TP12 TP13 LC-2S-Y LC-2S-Y SYMCLK BMPFS0
1 1
TP14 TP15 TP16 LC-2S-Y LC-2S-Y LC-2S-Y BMPFS1 DTVALID DAOUT0
1 1 1
TP17 LC-2S-Y LRCK0
1
TP18 LC-2S-Y BCK0
1
TP19 LC-2S-Y CLK
1
R71 R72
100 100 R73 100 R74 100 R75 100 R76 100 R77 22
EMPFS0 EMPFS1 DTVALID DAOUT0 LRCK0 BCK0 CLK
TP20 LC-2S-BK DGND
1
TP21 TP22 TP23 LC-2S-BK LC-2S-BK LC-2S-BK DGND DGND DGND
1 1 1
D2.5V D1.5V C52 0.1 C53 0.1
A2.5V
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
TEST10
TEST9
TEST8
TEST7
TEST6
DTVALID
TEST11 EMPFS1
EMPFS0
DAOUT
2
3
VR1 100
TP24 LC-2S-Y ADVRH
1
TEST5
LRCK
VDDE
BCK
VDDI
VSS
R78 27 1 2 3 4 C55 0.1 C56 10/16V A2.5V 5 6 7 8 C58 0.1 ADVIN 9 10 11 12 XRSTPW2 SWDIF0 SWDIF1 DTSEL 13 14 15
C54 0.1
TEST12 TEST13 TEST14 VDDE VSS ADVRH ADAVS ADAVD ADVRL ADVIN VDDE VSS XRST DIFM0
TEST4 TEST3 TEST2 TEST1 TEST0 OSCO VSS
48 D2.5V 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R80 100 TP25 LC-2S-Y SRDT
1
1
R79 10k Surface mount C57 8p
U8 CXD4017R Direct mount
VDDE OSCI VSS SCMODE SCLK XSCEN SWDT SRDT
30 DIVCODE 31 APX 28 VCOR 29 CHNUM
X1 12.288MHz
TEST16
APCPO
APAVD
24 APAVS 25 VSS
32 EXTCK
PLVAR
PLREF
APVCI
26 VDDI 27 VDDE
VSS
17
18
19
20
22
21
23
1
1
1
C64 0.1 Surface mount
1
- 27 -
C59 8p SCMODE SCLK XSCEN SWDT TP26 LC-2S-Y CSOD
DIFM1 16 TEST15
CSOD
C60 0.1
SRDT CSOD R81 100
TP27 LC-2S-Y PLREF
TP28 LC-2S-Y PLVAR
C61 0.1
C62 0.1
A1.5V R82 10k C63 0.1 R83 1k C65 1/35V T MSVA1V105M Surface mount R84 22 TP29 LC-2S-Y APX0
APX0
CXD4017R
SWCHNUM SWDIVCODE
CXD4017R EVB Circuit Diagram (MAIN)
D17 1S1588 U9
3
TP30 LC-2S-Y
2
LM317
ADJ
1
L1 SN3-200
ALT3.3V
VIN VOUT
TP31 LC-2S-Y L2 SN3-200
1
+D5V
R85 240
D18 1S1588 C68 47/16V C74 10/16V
C69 0.1
C66 0.1
C67 47/16V
2
3
1
J6 1 2 3 4 IL-4P-S3EN2
C70 10/16V
C71 0.1 JP3
C72 0.1
C73 47/16V
C75 10/16V
C76 0.1
L3 SN3-200
+A5V
D19 1S1588 U10
3
1
R86 270
R87 100
VR2 50
TP32 LC-2S-Y
2
LM317
ADJ
1
L4 SN3-200
D2.5V
C77 0.1
C78 47/16V
VIN VOUT
R88 240
TP33 LC-2S-BK AGND
1
TP34 LC-2S-Y
2
D20 1S1588 C81 47/16V C83 10/16V
C82 0.1
C79 0.1 L5 SN3-200
C80 47/16V A2.5V
3
1
R90 330 J7 1 2 D21 1S1588 U11
3
1
C86 0.1
C87 47/16V
1
1
ADJ
1
3
1
1
CXD4017R EVB Circuit Diagram (POWER)
1
- 28 -
L6 SN3-200
-A5V R89 560
VR3 200
C84 0.1
C85 47/16V
IL-2P-S3EN2 TP35 LC-2S-Y
2
JP1 TP36 LC-2S-Y
LM317
JP2 D22 1S1588
L7 SN3-200
A1.5V
VIN VOUT
R91 240
C90 47/16V
C91 0.1
C88 0.1
C89 47/16V
TP37 LC-2S-BK AGND
R92 220
2
VR4 200 R93 33
C92 10/16V
L8 SN3-200
D1.5V
C93 0.1
C94 47/16V
CXD4017R
+D5V R94 10k 1 2 3 4 C97 4.7/16V T C98 0.1
+D5V
+D5V
+D5V
+D5V
U12 Vref RESIN Ct GND VCC VsSENSE RESET RESET 8 7 6 5 R97 10k
C95 0.1
U13 R95 10k 1 2 3 4 C100 0.1 VCC VsSENSE RESET RESET TL7705CP Vref RESIN Ct GND 8 7 6 5 R98 10k
C96 0.1
R96 10k
SW1 AB-15AH
1 2 3
TL7705CP C99 4.7/16V T
td = 60ms
td = 60ms C101 0.1 U14 1 2 3 4 5 6 7 8 9 10 G1 VCC A1 G2 A2 Y1 A3 Y2 A4 Y3 A5 Y4 A6 Y5 A7 Y6 A8 Y7 GND Y8 20 19 18 17 16 15 14 13 12 11 XRSTPW2 XRSTPW1 TP38 TP39 LC-2S-Y LC-2S-Y
1
R99 100
1
- 29 -
D2.5V
XRSTPW1 XRSTPW2 R100 100
TC74LCX541F
CXD4017R EVB Circuit Diagram (RESET)
CXD4017R
A2.5V +A5V +A5V R101 4.7k
3
C102 0.1
C103 10/16V TP40 LC-2S-Y ADVIN
1
C104 0.1 R102 4.7k J8 SMB C106 0.1
VR5 5k 2
1
C105 0.1 Q1 2SC2223L
ADVIN R103 4.7k TP41 LC-2S-BK AGND
1
- 30 -
+A5V J9 1 2 3 IL-3P-S3EN2
R104 10k
R105 1k
DIVCODE
CXD4017R EVB Circuit Diagram (RFIN)
CXD4017R
CXD4017R
Pattern Diagram
CXD4017R EVB A Side Pattern Diagram
CXD4017R EVB B Side Pattern Diagram - 31 -
CXD4017R
CXD4017R EVB GND Layer Pattern Diagram
CXD4017R EVB Power Supply Layer Pattern Diagram - 32 -
CXD4017R
CXD4017R EVB A Side Silk Diagram
CXD4017R EVB B Side Silk Diagram - 33 -
CXD4017R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 10.0 0.1 + 0.2 1.5 - 0.1
48
33
49
32
A 64 17
1
0.5
16 b
0.08 M
0.08 S S
0.25
0.1 0.1
0.5 0.2 0.6 0.15
0.20 0.05
0.145 0.055
0 to 8 DETAIL A
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE JEITA CODE JEDEC CODE LQFP-64P-L023 P-LQFP64-10X10-0.5 TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 0.32g
LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. 42 ALLOY Sn-2%Bi 5-20m
- 34 -
Sony Corporation

▲Up To Search▲

Price & Availability of CXD4017R

	To Download CXD4017R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .